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19 Frequency Limits
Learning Objective
This exercise focuses on the analysis of the frequency limits of a transistor amplifier. The elements contributing to both the lower and upper limits of frequency performance are examined, thus defining the midband region of the circuit.
Theory Overview
As the signal frequency extends to very high or very low frequencies, capacitive effects on gain can no longer be ignored or idealized as shorts or opens. At low frequencies, coupling and bypass capacitors in conjunction with surrounding resistance create lead networks that cause a reduction in voltage gain. At higher frequencies, small shunting capacitances associated with individual devices and circuit wiring create lag networks. These will also create a reduction in voltage gain. In general, the highest critical frequency among the lead networks creates the amplifier’s lower limit frequency, f1. In contrast, the lowest critical frequency among the lag networks creates the amplifier’s upper limit frequency, f2. These points are defined as the half-power points and can be determined experimentally by finding those frequencies at which the output voltage (and hence, voltage gain) has fallen to 70.7% of the midband value. The values are found theoretically by Thevenizing the circuitry around the capacitor in question, reducing it to a single resistance, and solving for the critical frequency, fc.
Equipment
(1) Dual adjustable DC power supply
model:
srn:
(1) DMM
model:
srn:
(1) Dual channel oscilloscope
model:
srn:
(1) Function generator
model:
srn:
(1) Small signal transistor (2N3904)
(1) 10 k Ω resistor ¼ watt
actual:
(1) 15 k Ω resistor ¼ watt
actual:
(1) 20 k Ω resistor ¼ watt
actual:
(1) 33 k Ω resistor ¼ watt(1) 15 k Ω resistor ¼ watt
actual:
(1) 2.2 nF capacitor
actual:
(1) 10 nF capacitor
actual:
(2) 10 µF capacitors
actual:
(1) 470 µF capacitor
actual:
Schematic
Procedure
Midband Response
The circuit of Figure 1 is the same as the one used in the Common Emitter Amplifier exercise. The values used were Vcc = 15 volts, Vee = −12 volts, Rs = 10 kΩ, Rb = 33 kΩ, Re = 22 kΩ,Rc= 15 kΩ, Rload = 20 kΩ, C1 = C2 = 10 µF and C3 = 470 µF. It was shown that the amplifier produced considerable voltage at 1 kHz. Build the circuit using these values and verify that it is operating correctly by setting Vin to a 40 mV peak-peak sine wave at 1 kHz and measuring Vout. Compute the voltage gain and record these two values in Table 1.
Compute the expected critical frequencies of the input and output coupling networks along with the emitter bypass network and record the values in Table 2. Include the Thevenized resistance for each equivalent circuit.
Lower Frequency Limit
The input coupling network can be made clearly dominant by replacing C1 with a smaller value. Decreasing C1 from 10 µF to 10 nF will increase its critical frequency by a factor of 1000. Replace C1 with