KnowledgeHub
Questions
Tags
Users
Search
Alex Rivera
|
Logout
Edit Question
Title
Body
I'm trying to translate a Verilog program into VHDL and have stumbled across a statement where a question mark ( ? ) operator is used in the Verilog program. The following is the Verilog code; 1 module music(clk, speaker); 2 input clk; 3 output speaker; 4 parameter clkdivider = 25000000/440/2; 5 reg [23:0] tone; 6 always @(posedge clk) tone <= tone+1; 7 reg [14:0] counter; 8 always @(posedge clk) if(counter==0) counter <= (tone[23] ? clkdivider-1 : clkdivider/2-1); else counter <= counter-1; 9 reg speaker; 10 always @(posedge clk) if(counter==0) speaker <= ~speaker; 11 endmodule I don't understand the 8th line, could anyone please shed some light on this? I've read on the asic-world website that the question mark is the Verilog alternate for the Z character. But I don't understand why it's being used in this context. Kind regards
Tags (comma-separated)
Save Edits
Cancel