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Alex Rivera
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I have a Makefile which works perfectly called from a new shell, i.e.: make -C /dir/ However, if I call this Makefile from another Makefile, it fails due to some complicated dependency issues. Make clearly has knowledge of the nested calls, evident by the print of make[1]: etc, and I suspect make is somehow sharing variables with its child process. Is there anyway to call a clean make from within a Makefile? If my build works from a clean shell, it should be possible to call it from another Makefile without addressing the horrors inside the script! :) Thanks!
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