KnowledgeHub
Questions
Tags
Users
Search
Alex Rivera
|
Logout
Edit Question
Title
Body
How should I create a clock in a testbench? I already have found one answer, however others on stack overflow have suggested that there are alternative or better ways of achieving this: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY test_tb IS END test_tb; ARCHITECTURE behavior OF test_tb IS COMPONENT test PORT(clk : IN std_logic;) END COMPONENT; signal clk : std_logic := '0'; constant clk_period : time := 1 ns; BEGIN uut: test PORT MAP (clk => clk); -- Clock process definitions( clock with 50% duty cycle is generated here. clk_process :process begin clk <= '0'; wait for clk_period/2; --for 0.5 ns signal is '0'. clk <= '1'; wait for clk_period/2; --for next 0.5 ns signal is '1'. end process; END; (source here )
Tags (comma-separated)
Save Edits
Cancel