How to instruct Makefile to use different compilers

I have to build my code for two different platforms at once using two different compilers and libraries. How can I do this with single make file.

Currently my makefile contents are given below. How can I instruct it to change the compiler to gcc within the same makefile?

VPATH = /root/Documents/project/src 

CROSS_COMPILE  = /opt/compilers/bin/compiler1
CXX = $(CROSS_COMPILE)-g++
CC = $(CROSS_COMPILE)-gcc
AS = $(CROSS_COMPILE)-as
AR = $(CROSS_COMPILE)-ar
NM = $(CROSS_COMPILE)-nm
LD = $(CROSS_COMPILE)-ld
OBJDUMP = $(CROSS_COMPILE)-objdump
OBJCOPY = $(CROSS_COMPILE)-objcopy
RANLIB = $(CROSS_COMPILE)-ranlib
STRIP = $(CROSS_COMPILE)-strip


CFLAGS       = -c -Wall -D_REENTRANT -DACE_HAS_AIO_CALLS -D_GNU_SOURCE -DACE_HAS_EXCEPTIONS -D__ACE_INLINE__  
LDFLAGS      = -L. -L/etc/ACE_wrappers/lib 
CPPFLAGS     += -I/etc/ACE_wrappers -I/etc/ACE_wrappers/ace 
LDLIBS       = -lACE

OUTPUT_DIRECTORY=/root/Documents/bin
OBJ=/root/Documents/obj

ifneq ($(OUTPUT_DIRECTORY),)
all: $(OUTPUT_DIRECTORY)
$(OUTPUT_DIRECTORY):
    -@$(MKDIR) "$(OUTPUT_DIRECTORY)"
endif

ifneq ($(OBJ),)
all: $(OBJ)
$(OBJ_DIR):
    -@$(MKDIR) "$(OBJ)"
endif

SOURCES=File_1.cpp File_2.cpp 

OBJECTS=$(SOURCES:%.cpp=$(OBJ)/%.o)

$(OBJ)/%.o: %.cpp
    @echo Building Objects
    $(CC) $(CFLAGS) $(CPPFLAGS) $(CXXFLAGS) -c -o $@ $<


EXECUTABLE=MyExecutable

all: $(SOURCES) $(EXECUTABLE)

$(EXECUTABLE): $(OBJECTS) 
    @echo $(SOURCES)
    $(CC) $(LDFLAGS) $(OBJECTS) $(LDLIBS) -o $(OUTPUT_DIRECTORY)/$@

File_1.o:File_1.cpp
File_1.o:File_1.cpp


.PHONY: clean
clean:
    rm $(OBJECTS) $(OUTPUT_DIRECTORY)/$(EXECUTABLE)