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This is my current makefile. CXX = g++ CXXFLAGS = -Wall -O3 LDFLAGS = TARGET = testcpp SRCS = main.cpp object.cpp foo.cpp OBJS = $(SRCS:.cpp=.o) DEPS = $(SRCS:.cpp=.d) .PHONY: clean all all: $(TARGET) $(TARGET): $(OBJS) $(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJS) -o $(TARGET) .cpp.o: $(CXX) $(CXXFLAGS) -c $< -o $@ %.d: %.cpp $(CXX) -M $(CXXFLAGS) $< > $@ clean: rm -f $(OBJS) $(DEPS) $(TARGET) -include $(DEPS) It works perfectly with one exception. If the directory is already clean (no *.d, *.o) and I run 'make clean', it re-creates the dependencies, then immediately deletes them: [user@server proj]$ make g++ -M -Wall -O3 foo.cpp > foo.d g++ -M -Wall -O3 object.cpp > object.d g++ -M -Wall -O3 main.cpp > main.d g++ -Wall -O3 -c main.cpp -o main.o g++ -Wall -O3 -c object.cpp -o object.o g++ -Wall -O3 -c foo.cpp -o foo.o g++ -Wall -O3 main.o object.o foo.o -o testcpp [user@server proj]$ make clean rm -f main.o object.o foo.o main.d object.d foo.d testcpp [user@server proj]$ make clean g++ -M -Wall -O3 foo.cpp > foo.d g++ -M -Wall -O3 object.cpp > object.d g++ -M -Wall -O3 main.cpp > main.d rm -f main.o object.o foo.o main.d object.d foo.d testcpp [user@server proj]$ I don't understand why the second 'make clean' would re-generate the dependency files. How can I avoid this? This isn't a big deal for this contrived example, but for a large project, it can be quite time-consuming. Thanks.

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