KnowledgeHub
Questions
Tags
Users
Search
Alex Rivera
|
Logout
Edit Question
Title
Body
I am implementing a configurable DPRAM where RAM DEPTH is the parameter. How to determine ADDRESS WIDTH from RAM DEPTH? I know the relation RAM DEPTH = 2 ^ (ADDRESS WIDTH) i.e ADDRESS WIDTH = log (base 2) RAM DEPTH. How to implement the log (base 2) function in Verilog?
Tags (comma-separated)
Save Edits
Cancel