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A few months ago, I came up with the following generic Makefile for school assignments: # ------------------------------------------------ # Generic Makefile # # Author: yanick.rochon@gmail.com # Date : 2010-11-05 # # Changelog : # 0.01 - first version # ------------------------------------------------ # project name (generate executable with this name) TARGET = projectname CC = gcc -std=c99 -c # compiling flags here CFLAGS = -Wall -I. LINKER = gcc -o # linking flags here LFLAGS = -Wall SOURCES := $(wildcard *.c) INCLUDES := $(wildcard *.h) OBJECTS := $(SOURCES:.c=*.o) rm = rm -f $(TARGET): obj @$(LINKER) $(TARGET) $(LFLAGS) $(OBJECTS) @echo "Linking complete!" obj: $(SOURCES) $(INCLUDES) @$(CC) $(CFLAGS) $(SOURCES) @echo "Compilation complete!" clean: @$(rm) $(TARGET) $(OBJECTS) @echo "Cleanup complete!" This will basically compile every .c and .h file to generate .o files and the executable projectname all in the same folder. Now, I'd like to push this a little. How can I write a Makefile to compile a C project with the following directory structure? ./ ./Makefile ./src/*.c;*.h ./obj/*.o ./bin/<executable> In other words, I'd like to have a Makefile that compiles C sources from ./src/ into ./obj/ and then link everything to create the executable in ./bin/ . I've tried to read different Makefiles, but I simply can't make them work for the project structure above; instead, the project fails to compile with all sorts of errors. Sure, I could use full blown IDE (Monodevelop, Anjuta, etc.), but I honestly prefer to stick with gEdit and the good ol' terminal. Is there a guru who can give me a working solution, or clear information about how this can be done? Thank you! ** UPDAT

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