How can I separate long statements into lines in Verilog

For example, I have a single long statement:

    $display("input_data: %x, 
              output_data: %x,
              result: %x",
              input_data,
              output_data,
              result);

How can I make it into single statement and multiple lines in Verilog?

verilog system-verilog

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How can I separate long statements into lines in Verilog

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