I'm completely new to Verilog, so bear with me.

I'm wondering if there is an assert statement in Verilog. In my testbench, I want to be able to assert that the outputs of modules are equal to certain values.

For example,

mymodule m(in, out);
assert(out == 1'b1);

Googling gave me a few links, but they were either too complex or didn't seem to be what I wanted.

assert verilog
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