Verilog sequence of non blocking assignments

Say the following code section (same block):

A <= 1
A <= 2

Will variable A always be assigned 2? or will there be a race condition and 1 or 2 will be assigned ?

My understanding of non blocking assignment is that it is up to the hardware to assign the variable A at a future time so it could be a random result. However, this is non intuitive. Simulations show that 2 always get assigned, but I would like to know if this is definitely the case for hardware synthesis.