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Questions tagged cpu-architecture

41 questions

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12
votes
1
answers

What does the ".align" directive mean in x86-64 Assembly?

assembly x86 x86-64 cpu-architecture
asked 2013-06-25T19:15:33.730
14
votes
2
answers

Why are CISC processors harder to pipeline? In what sense are some instructions "more complex" than others?

x86 cpu-architecture instruction-set pipelining
asked 2013-06-25T02:51:38.027
12
votes
6
answers

Seeing how Instructions get Translated (Computer Architecture)

assembly embedded emulation cpu-architecture 6502
asked 2013-04-18T12:22:02.347
54
votes
4
answers

How does direct mapped cache work?

caching system cpu-architecture
asked 2013-04-10T21:44:12.460
16
votes
2
answers

CPU cache behaviour/policy for file-backed memory mappings?

c++ x86 operating-system cpu-architecture cpu-cache
asked 2013-04-06T16:53:23.873
29
votes
5
answers

What is the point of delay slots?

assembly mips cpu-architecture branch-prediction pipelining
asked 2013-03-13T00:50:22.413
266
votes
5
answers

How does the ARM architecture differ from x86?

x86 arm cpu-architecture
asked 2013-02-10T03:39:59.850
12
votes
1
answers

Return stack buffer?

x86 cpu cpu-architecture branch-prediction micro-architecture
asked 2012-12-05T12:08:28.847
51
votes
2
answers

Is x86 RISC or CISC?

x86 cpu cpu-architecture
asked 2012-10-25T14:48:11.940
20
votes
1
answers

OS X arch command incorrect

macos cpu-architecture
asked 2012-10-06T19:54:01.133
42
votes
8
answers

How to find the size of the L1 cache line size with IO timing measurements?

c++ c performance caching cpu-architecture
asked 2012-10-01T14:19:09.187
27
votes
1
answers

Difference between armeabi and armeabi-v7a

android android-ndk cpu-architecture freepascal abi
asked 2012-08-31T16:24:01.250
46
votes
9
answers

API call to get processor architecture

android cpu-architecture
asked 2012-08-16T14:39:54.470
57
votes
6
answers

Why is the page size of Linux (x86) 4 KB, how is that calculated?

linux x86 cpu-architecture paging virtual-memory
asked 2012-07-18T14:30:28.543
58
votes
1
answers

what is a store buffer?

architecture hardware intel cpu-architecture
asked 2012-06-19T17:03:28.910
37
votes
4
answers

Cycles/cost for L1 Cache hit vs. Register on x86?

performance x86 cpu-architecture cpu-cache micro-optimization
asked 2012-04-23T03:08:11.003
17
votes
3
answers

Can two processes simultaneously run on one CPU core?

cpu-architecture multicore multitasking hyperthreading
asked 2012-01-18T20:10:53.077
74
votes
7
answers

how much memory can be accessed by a 32 bit machine?

32bit-64bit ram cpu-architecture
asked 2012-01-15T12:19:40.657
14
votes
5
answers

Difference between memory bus and address bus

cpu-architecture pci-e bus pci-bus
asked 2011-11-15T10:04:52.743
10
votes
6
answers

AND faster than integer modulo operation?

assembly arm cpu-architecture micro-optimization
asked 2011-10-06T16:11:00.160
9
votes
2
answers

What does func means in R-Format instruction set?

assembly mips cpu-architecture machine-code
asked 2011-08-03T15:56:35.000
154
votes
11
answers

Why do x86-64 systems have only a 48 bit virtual address space?

x86-64 virtual-memory cpu-architecture
asked 2011-07-16T11:09:23.487
14
votes
4
answers

in what architectures/OS other thread can see default nonfinal field values after constructor call?

java multithreading constructor cpu-architecture memory-visibility
asked 2011-06-09T14:50:21.927
120
votes
16
answers

Are there any smart cases of runtime code modification?

executable cpu-architecture instructions self-modifying platform-agnostic
asked 2011-04-04T07:16:12.647
9
votes
4
answers

Why are there so many CPU architectures: x86, x64, x87, etc...?

cpu-architecture
asked 2011-03-30T03:00:51.287
19
votes
4
answers

Does anyone know any Compiler which optimizes code for energy consumption for embedded devices?

compilation cpu-architecture energy
asked 2011-01-20T11:17:17.917
29
votes
4
answers

Why does CPU access memory on a word boundary?

c assembly memory cpu-architecture memory-alignment
asked 2010-09-07T05:06:34.223
10
votes
6
answers

Python: get windows OS version and architecture

python windows cpu-architecture
asked 2010-05-04T10:05:35.460
9
votes
3
answers

Detecting architecture at compile time from MASM/MASM64

assembly x86-64 cpu-architecture masm masm32
asked 2010-04-07T20:08:33.953
112
votes
4
answers

What is the cost of atomic operations?

performance atomic cpu-architecture lock-free
asked 2010-03-29T13:11:25.180
12
votes
10
answers

Assembler : why BCD exists?

assembly x86 cpu-architecture dataformat bcd
asked 2010-03-01T22:21:17.683
57
votes
9
answers

What are some examples of non-Von Neumann architectures?

cpu-architecture von-neumann
asked 2009-11-27T02:25:09.407
17
votes
4
answers

Understanding word alignment

algorithm hardware theory cpu-architecture
asked 2009-10-18T07:38:04.773
45
votes
19
answers

Porting 32 bit C++ code to 64 bit - is it worth it? Why?

c++ x86 64-bit x86-64 cpu-architecture
asked 2009-09-25T23:24:49.160
15
votes
5
answers

Most portable library for dynamic code generation?

c++ assembly code-generation cpu-architecture machine-code
asked 2009-09-11T23:35:48.837
12
votes
6
answers

Are Harvard architecture computers immune to arbitrary code injection and execution attacks?

security cpu-architecture harvard-architecture
asked 2009-06-05T06:50:53.960
19
votes
4
answers

Setup targeting both x86 and x64?

c# installation cpu-architecture
asked 2009-04-15T19:51:47.073
19
votes
4
answers

How are interrupts handled by dual processor machines?

hardware cpu multicore interrupt cpu-architecture
asked 2009-03-01T04:05:15.383
20
votes
15
answers

Exactly how "fast" are modern CPUs?

performance assembly x86 cpu-architecture cpu-speed
asked 2009-01-11T15:53:26.853
20
votes
9
answers

Where are variables in C++ stored?

c++ architecture memory cpu-architecture
asked 2008-10-23T17:14:55.597
9
votes
5
answers

How cache memory works?

c caching optimization cpu-architecture
asked 2008-10-20T11:36:51.537