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Questions tagged vhdl

14 questions

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38
votes
4
answers

VHDL - How should I create a clock in a testbench?

simulation vhdl clock hardware
asked 2013-07-28T02:47:07.153
9
votes
4
answers

VHDL: creating a very slow clock pulse based on a very fast clock

vhdl clock fpga
asked 2013-03-06T10:37:39.490
8
votes
3
answers

Why do we use functions in VHDL

vhdl
asked 2013-01-21T17:22:07.280
15
votes
5
answers

VHDL: use the length of an integer generic to determine number of select lines

generics vhdl
asked 2012-10-05T16:04:26.127
13
votes
3
answers

Verilog question mark (?) operator

operators vhdl verilog
asked 2012-09-09T02:48:06.697
10
votes
3
answers

Is there a VHDL equivalent to Verilog's @(*), i.e., automatic process sensitivity list

vhdl
asked 2011-03-21T22:01:02.007
17
votes
3
answers

How does signal assignment work in a process?

vhdl modelsim
asked 2011-02-20T22:48:08.627
17
votes
3
answers

What to use for VHDL/digital-logic simulation on Mac OS X

macos simulation vhdl digital-logic
asked 2011-01-25T10:23:18.707
22
votes
5
answers

Error adding std_logic_vectors

vhdl fpga
asked 2010-10-28T12:20:43.623
22
votes
7
answers

Creating a VHDL backend for LLVM?

llvm vhdl
asked 2010-09-08T04:44:28.607
15
votes
5
answers

Better ways to implement a modulo operation (algorithm question)

algorithm modulo vhdl
asked 2010-05-05T13:33:53.607
12
votes
6
answers

Which programming language has very short context-free Grammar in its formal specification?

python c bash vhdl
asked 2009-11-21T22:32:01.173
10
votes
5
answers

Program for drawing VHDL block diagrams?

diagram vhdl
asked 2009-07-20T22:09:46.363
15
votes
6
answers

Microcontroller + Verilog/VHDL simulator?

microcontroller simulator verilog vhdl
asked 2008-12-17T19:23:59.277